1. Field of the Invention
The present invention relates to a so-called virtual ground (VG) type semiconductor memory device comprising a memory cell array in which active regions (for example channel forming regions in nonvolatile memory transistors) and impurity regions (for example source and drain impurity regions in the bit line direction) shared by adjacent memory cells are provided alternately in a word line direction, and a method of operation thereof.
2. Description of the Related Art
In a VG type memory cell array structure, in the vicinity of the surface of a p-well formed in the main surface of a semiconductor substrate or a p-type semiconductor substrate, not element isolation layers, but just long n+ impurity regions (source and drain impurity regions) are repeatedly formed along a bit line direction at certain intervals in a word line direction in the form of parallel stripes.
In the vicinity of the surface of the p-well between the source and drain impurity regions, gate electrodes are stacked on a number of insulating films including charge storing means in the films or between the films. Therefore, the vicinity of the surface of the p-well functions as a channel forming region of a memory transistor.
In a floating gate (FG) type, on the gate insulating film at the bottom, a floating gate comprised of a conductive film is formed serving as a charge storing means, and above that, control gates are formed on an inter-gate insulating film comprised of an oxide-nitride-oxide (ONO) film. Usually, the control gates are also used as word lines commonly provided between memory transistors in the word line direction.
On the other hand, in a metal-oxide-nitride-oxide-semiconductor (MONOS) type, a gate electrode is formed directly on a channel forming region with an ONO film in between. In this case, the carrier traps dispersed in the boundary between a nitride film and an oxide film in the ONO film and in the nitride film work as charge storing regions. Other devices that employ such a charge forming means dispersed in a plane facing the channel and in the thickness direction include an MNOS type, a nanocrystal type, and so on. When using gate electrodes also as word lines, gate electrodes formed using isolated patterns sometimes are connected to an upper metal interconnection layer to act as word lines.
In each of the above types, the source and drain impurity regions described above function as bit lines or sub-bit lines connected with the upper layer main bit lines. In addition, the word lines are usually arranged in the form of parallel stripes intersecting with the source and drain impurity regions.
In a VG type memory cell array configured in this way, because the element isolation layers are unnecessary and the source and drain impurity regions are shared by two adjacent cells in the word line direction, there is the advantage that its memory cell area is the smallest among the many memory cell array structures.
In a VG type memory cell array, when writing or reading a memory transistor connected to a word line, a specified read drain voltage or write drain voltage is applied between two source and drain impurity regions adjoining the channel forming region of this memory transistor.
The source and drain impurity regions, however, are shared with an adjoining nonselected memory transistor in the word line direction, so the applied voltage influences the voltage on the other source and the other drain impurity regions positioned at the other sides (referred to as outside) of these nonselected memory transistors. That is, to prevent unintentional operations of the two adjoining nonselected memory transistors that share the same word line with a selected memory transistor, a voltage the same as that applied to the adjacent inside source and drain has to be applied to the two source and drain impurity regions positioned at the outsides. This is true also for the source and drain impurity regions further outside and still further outside. Therefore, once the voltage on the source and drain impurity regions of a memory transistor is defined, it influences the other outside source and drain impurity regions connected to the same word line one after another until the memory transistor at the end of the memory cell array.
Because of the above difficulty in voltage setting, in a VG type memory cell array of the related art, even if random access enabling selection of any of the plurality of memory transistors connected to a single word line is possible, serial access for simultaneously accessing a number of memory transistors is not possible. Even it is attained, it is possible only when the restriction on voltage setting is fulfilled coincidentally. This conditional access is not practical. Therefore, in a VG type memory cell array of the related art, it is not possible to freely and independently operate a plurality of memory transistors connected to a single word line.
As a result, in a nonvolatile memory device employing a VG type memory cell array of the related art, simultaneous operations of a word line or operations at a high speed close to that are not possible. Although such a device is suitable for applications requiring large capacities because of its low cost per bit, it suffers from the disadvantage that it cannot be used for applications requiring high speeds.
An object of the present invention is to provide a semiconductor memory device having a virtual ground type memory cell array capable of parallel write and read operations of a plurality of memory transistors connected to a word line and a method of operation thereof.
According to a first aspect of the present invention, there is provided a method for operating a semiconductor memory device comprising a memory cell array including a plurality of memory cells each having, alternately provided in a word line direction, an active region comprised of a first conductivity type semiconductor and impurity regions comprised of a second conductivity type semiconductor shared with adjacent memory cells; word lines capacitively coupled with the active regions; and control gates capacitively coupled with the borders of the active regions with the impurity regions and electrically isolated from the word line, the method comprising the steps of driving the control gates to electrically divide the memory cell array in the word line direction and driving the impurity regions and the word lines in the divided memory cell array to write, read, or erase the plurality of memory cells in parallel.
Preferably, a control gate is provided, for each impurity region, partly overlapping two active regions adjoining the two sides of the impurity region in the word line direction, and the method further comprises, in said step of the division, a step of applying a specific cutoff voltage on the control gate at the division point to set the control gate OFF and changing the borders of the two active regions from an electrical connection state to a cutoff state.
In this case, the number of memory cells connected to one word line is J times an integer n not less than 3, and the method further comprises a step of dividing the memory cell array into n number of memory cell arrays each including J number of memory cells according to the combination of the control gates that are set ON.
Alternatively, the word lines are comprised of i number of sub word lines (i is an integer not less than 2) and a main word line to which the i number of sub word lines are commonly connected, the number of memory cells connected to each sub word line is J times an integer n not less than 3, and the method further comprises a step of driving the control gates to electrically divide the memory cell array into n number of memory cell arrays each including J number of memory cells for each sub word line and totally (Jxc3x97i) number of memory cells in the word line direction.
Specifically, the method further comprises, when electrically dividing one physical memory cell array into n number of memory cell arrays (n is an integer not less than 3), the steps of making a group of control gates in which two control gates are set ON and the following (nxe2x88x922) are set OFF and cyclically repeating this set of electrical states of the group of n number of control gates in the word line direction.
The method further comprises, at the same time as the division, a step of selecting a memory cell array including a plurality of discrete memory cells capable of parallel operation.
Alternatively, the method further comprises a step of shifting the positions of the control gates in an OFF state each time by one for every (nxe2x88x921) number of times in the word line direction in order to enable selection of the n (n is an integer not less than 3) number of divided memory cell arrays one after another. The method further comprises, each time the electrical state of the control gates is shifted by one in the word line direction, the steps of selecting a word line again and simultaneously writing, reading, or erasing the memory cells in parallel again in an electrically divided and selected memory cell array among the memory cells connected to the selected word line.
On the other hand, in the present invention, a first control gate partly overlapping the active region in the vicinity of the border with an impurity region adjoining one side of the active region and a second control gate partly overlapping the active region in the vicinity of the border with another impurity region adjoining the other side of the active region may be provided in pairs, and the method may further comprise a step of changing the borders of the corresponding active region from an electrical connection state to a cutoff state when the first and second control gates are set OFF.
In this case, preferably the number of memory cells connected to one word line is K times an integer m not less than 2, an the method further comprises, for each word line, a step of dividing the memory cell array into m number of memory cell arrays each including K number of memory cells according to the combination of the control gates set OFF.
Specifically, for example, when electrically dividing one physical memory cell array into m number of memory cell arrays (m is an integer not less than 2), the method further comprises the steps of selecting one group of the first control gates or one group of the second control gates on the word line, making a group of control gates in which one control gate in the selected group is set ON and the following (mxe2x88x921) control gates in the same group are set OFF, cyclically repeating this set of electrical states of the group of m control gates in the selected word line direction, and setting all control gates in nonselected groups ON.
The method further comprises, at the same time as the division, a step of selecting a memory cell array including a plurality of discrete memory cells capable of parallel operation.
Alternatively, the method further comprises a step of shifting the position of the first or the second control gate in an OFF state in the selected group each time by one (mxe2x88x921) number of times in the word line direction in order to enable selection of the m (not less than 2) number of divided memory cell arrays one after another. Further, the method further comprises, each time the electrical state of the control gate is shifted by one in the word line direction in the selected group, the steps of selecting a word line again and simultaneously writing, reading, or erasing the memory cells in parallel again in an electrically divided and selected memory cell array among the memory cells connected to the selected word line.
Alternatively, the method further comprises, when electrically dividing one physical memory cell array into m number of memory cell arrays (m is an integer not less than 2), the steps of making a group of a first and a second control gates by setting ON the first and second control gates sandwiching an active region capacitively coupled with said word line and positioned at two sides of the active region in the word line direction, and by setting OFF the following (mxe2x88x921) pairs of the first and second control gates and cyclically repeating this set of electrical states of the 2m number of control gates in the word line direction.
The method further comprises, at the same time of the division, a step of selecting a memory cell array including a plurality of discrete memory cells capable of parallel operation.
Alternatively, the method further comprises a step of shifting the positions of the first and second control gates in an ON state each time by two (mxe2x88x921) number of times in the word line direction in order to enable selection of the m (not less than 2) number of divided memory cell arrays one after another. The method further comprises, each time the electrical state of the control gates is shifted by two in the word line direction, the steps of selecting a word line again and simultaneously writing, reading, or erasing the memory cells in parallel again in an electrically divided and selected memory cell array among the memory cells connected to the selected word line.
In the method for operating a semiconductor memory device according to the first aspect of the present invention, one physical virtual ground type memory cell array is divided into a number of memory cell arrays for operation. Each memory cell array, for example, is comprised of memory cells discretely extracted out of every at least two or three memory cells. In the present invention, the discrete memory cells in one memory cell array are operated, i.e., written in, read, or erased, at one time. After the parallel operation, the selectable memory cell array is changed by shifting the division points in the word line direction to operate the memory cells in other memory cell arrays simultaneously in a similar way. As a result, by repeating the change of the selectable memory cell array and the parallel operation for the number of times the same as the number of divisions, all the memory cells in a memory cell array are written, read, or erased.
According to a second aspect of the present invention, there is provided a semiconductor memory device comprising a memory cell array including a plurality of memory cells, each having, alternately provided in a word line direction, an active region comprised of a first conductivity type semiconductor and impurity regions comprised of a second conductivity type semiconductor shared by adjacent memory cells; word lines capacitively coupled with the active regions; control gates capacitively coupled with the borders of the active regions with the impurity regions and electrically isolated from the word lines; and a control circuit for driving the control gates to electrically divide the memory cell array in the word line direction and driving the impurity regions and the word lines in the divided memory cell array to write, read, or erase the plurality of memory cells in parallel.
Preferably, a control gate is provided, for each impurity region, partly overlapping two active regions adjoining the two sides of the impurity region in the word line direction, and the control circuit changes the borders of the two active regions from an electrical connection state to a cutoff state when the control gate is set OFF. In this case, preferably, the memory cell is comprised of a nonvolatile memory transistor, the nonvolatile memory transistor comprises a plurality of gate insulating films formed on the active region in which a channel of the transistor is formed and including a charge storing means in films or between films and gate electrodes commonly connected by the word line, the control gate is provided on the plurality of gate insulating films, and comprises a conductive layer buried in the space between gate electrodes with an insulating film in between.
Alternatively, a first control gate partly overlapping the active region in the vicinity of the border of the active region with an impurity region adjoining one side of the active region and a second control gate partly overlapping the active region in the vicinity of the border of the active region with another impurity region adjoining the other side of the active region are provided in pairs, and the control circuit changes the borders of the corresponding active regions from an electrical connection state to a cutoff state when the first and second control gates are set OFF.
In this case, the memory cell is comprised of a nonvolatile memory transistor, the nonvolatile memory transistor comprises a plurality of gate insulating films formed on the active region in which a channel of the transistor is formed and including a charge storing means in films or between films and gate electrodes commonly connected by the word line, and the first and second control gates comprise two conductive layers separated from each other and formed on the plurality of gate insulating films between the gate electrodes with insulating films on their side surfaces facing each other.
In a semiconductor memory device including memory transistors having such a configuration, the control gate comprises a conductive layer buried in the space between gate electrodes or conductive layers formed between the gate electrodes with insulating films on their side surfaces facing each other. Consequently, provision of the control gates does not increase the size of a transistor.